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preliminary 4-mbit (128k x 36) flow-through sram with nobl? architecture cy7c1351g cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05513 rev. *a revised october 14, 2004 features ? can support up to 133-mhz bus operations with zero wait states ? data is transferred on every clock ? pin compatible and functionally equivalent to zbt? devices ? internally self-time d output buffer cont rol to eliminate the need to use oe ? registered inputs for flow-through operation ? byte write capability ? 128k x 36 common i/o architecture ? 2.5v / 3.3v i/o power supply ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? 7.5 ns (for 117-mhz device) ? 8.0 ns (for 100-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? asynchronous output enable ? lead-free 100 tqfp and 119 bga packages ? burst capability?linear or interleaved burst order ? low standby power functional description [1] the cy7c1351g is a 3.3v, 128k x 36 synchronous flow-through burst sram designed specifically to support unlimited true back-to-back read/w rite operations without the insertion of wait states. the cy7c1351g is equipped with the advanced no bus latency? (nobl?) logic required to enable consecutive read/write op erations with data being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133-mhz device). write operations are controlled by the four byte write select (bw [a:d] ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during the data portion of a write sequence. note: 1. for best?practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. logic block diagram c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
preliminary cy7c1351g document #: 38-05513 rev. *a page 2 of 14 selection guide 133 mhz 117 mhz 100 mhz unit maximum access time 6.5 7.5 8.0 ns maximum operating current 225 220 205 ma maximum cmos standby current 40 40 40 ma shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. pin configurations 100-lead tqfp a a a a a1 a0 nc nc v ss v dd nc a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a nc adv/ld zz mode nc cy7c1351g byte a byte b byte d byte c
preliminary cy7c1351g document #: 38-05513 rev. *a page 3 of 14 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the 128k address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw [a:d] input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 , and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to co ntrol the direction of the i/o pins. wh en low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pi ns are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequ ence, during the first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock si gnal is recognized by the sram. when deasserted high the clock si gnal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. pin configurations (continued) 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aa nc v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc nc nc nc nc nc nc nc v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adv/ld nc ce 1 oe nc we v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c v ss v dd v ss bw a nc cen bw d zz 119-ball bga a
preliminary cy7c1351g document #: 38-05513 rev. *a page 4 of 14 functional overview the cy7c1351g is a synchronous flow-through burst sram designed specifically to el iminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw [a:d] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another oper ation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. burst read accesses the cy7c1351g has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst coun ter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incremented su fficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. ther efore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regar dless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp [a:d] . on the next clock rise the data presented to dqs and dqp [a:d] (or a subset for byte write o perations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the wr ite operation is controlled by bw [a:d] signals. the cy7c1351g provides byte write capability that is described in the truth table. asserting the write enable input (we ) with the selected byte write select zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, this pin can be connected to vss or left floating. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-c hip data register t hat is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by address during the clock rise of the read cycle. the dire ction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq s and dqp [a:d] are placed in a tri-state conditi on. the outputs are automatically tri-stated during the data portion of a write sequ ence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp [a:d] i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq s . during write sequences, dqp [a:d] is controlled by bw [a:d] correspondingly. mode input strap pin mode input. selects the burst order of the device . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . nc ? no connects . not internally connected to the die. pin definitions (continued) name i/o description
preliminary cy7c1351g document #: 38-05513 rev. *a page 5 of 14 input will selectively write to on ly the desired bytes. bytes not selected during a byte write oper ation will remain unaltered. a synchronous self-timed write me chanism has been provided to simplify the write operations . byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write opera- tions. because the cy7c1351g is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp [a:d] inputs. doing so will tri-state the output driver s. as a safety precaution, dqs and dqp [a:d] .are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1351g has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in th e single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counte r is incremented. the correct bw [a:d] inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. linear burst address table (mode = gnd) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to snooze current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze curre nt this parameter is sampled 0 ns truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state notes: 2. x = don?t care.? h= logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 3. write is defined by bw x , and we . see truth table for read/write. 4. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 5. the dqs and dqp [a:d] pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with t he clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp [a:d] = tri-state when oe is inactive or when the device is deselected, and dqs and dqp [a:d] = data when oe is active.
preliminary cy7c1351g document #: 38-05513 rev. *a page 6 of 14 write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burs t) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h ? snooze mode none x x x h x x x x x x tri-state partial truth table for read/write [2, 3, 9] function we bw a bw b bw c bw d read h x x x x read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a )llhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d ) lhhh l write all bytes l l l l l note: 9. table only lists a partial listing of the by te write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active. truth table (continued) [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq
preliminary cy7c1351g document #: 38-05513 rev. *a page 7 of 14 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on vdd relative to gnd ...... ?0.5v to +4.6v dc voltage applied to outputs in tri-state ............................................ ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature (t a )v dd v ddq com?l 0c to +70c 3.3v - 5%/+10% 2.5v - 5% to v dd ind?l ? 40c to +85c electrical characteristics over the operating range [10,11] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3v v input high voltage v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [10] v ddq = 3.3v ?0.3 0.8 v input low voltage [10] v ddq = 2.5v ?0.3 0.7 v i x input load current (except zz and mode) gnd v i v ddq ? 55 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v dd , output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 225 ma 8.5-ns cycle, 117 mhz 220 ma 10-ns cycle, 100 mhz 205 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = f max , inputs switching 7.5-ns cycle, 133 mhz 90 ma 8.5-ns cycle, 117 mhz 85 ma 10-ns cycle, 100 mhz 80 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 40 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 75 ma 8.5-ns cycle, 117 mhz 70 ma 10-ns cycle, 100 mhz 65 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 45 ma shaded areas contain advance information. notes: 10. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> -2v (pulse width less than t cyc /2). 11. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd .
preliminary cy7c1351g document #: 38-05513 rev. *a page 8 of 14 thermal resistance [12] parameters description test conditions tqfp package bga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w capacitance [12] parameter description test conditions tqfp package bga package unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 3.3v v ddq =3.3v 55pf c clock clock input capacitance 5 5 pf c i/o i/o capacitance 5 7 pf ac test loads and waveforms note: 12. tested initially and after any design or proc ess changes that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1351g document #: 38-05513 rev. *a page 9 of 14 switching characteristics over the operating range [17, 18] parameter description 133 mhz 117 mhz 100 mhz unit min. max. min. max. min. max. t power v dd (typical) to the first access [13] 1 1 1 ms clock t cyc clock cycle time 7.5 8.5 10 ns t ch clock high 2.5 3.0 4.0 ns t cl clock low 2.5 3.0 4.0 ns output times t cdv data output valid after clk rise 6.5 7.5 8.0 ns t doh data output hold after clk rise 2.0 2.0 2.0 ns t clz clock to low-z [14, 15, 16] 0 0 0 ns t chz clock to high-z 14, 15, 16] 3.5 3.5 3.5 ns t oev oe low to output valid 3.5 3.5 3.5 ns t oelz oe low to output low-z [14, 15, 16] 0 0 0 ns t oehz oe high to output high-z [14, 15, 16] 3.5 3.5 3.5 ns set-up times t as address set-up before clk rise 1.5 2.0 2.0 ns t als adv/ld set-up before clk rise 1.5 2.0 2.0 ns t wes we , bw x set-up before clk rise 1.5 2.0 2.0 ns t cens cen set-up before clk rise 1.5 2.0 2.0 ns t ds data input set-up before clk rise 1.5 2.0 2.0 ns t ces chip enable set-up before clk rise 1.5 2.0 2.0 ns hold times t ah address hold after clk rise 0.5 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 0.5 ns shaded areas contain advance information. notes: 13. this part has a voltage regulator internally; tpower is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 14. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac te st loads. transition is measured 200 mv from steady-state vo ltage. 15. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention co ndition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve tri-state prior to low- z under the same system conditions 16. this parameter is sampled and not 100% tested. 17. timing reference level is 1.5v when v ddq =3.3v and is 1.25v when v ddq = 2.5v. 18. test conditions shown in (a) of ac test loads, unless otherwise noted.
preliminary cy7c1351g document #: 38-05513 rev. *a page 10 of 14 switching waveforms read/write waveforms [19, 20, 21 ] nop, stall and deselect cycles [19, 20, 22] notes: 19. for this waveform zz is tied low. 20. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 21. order of the burst sequence is determined by the status of th e mode (0= linear, 1= interleaved). burst operations are option al. 22. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw [a:d] adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:d] adv/ld address dq c ommand write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5)
preliminary cy7c1351g document #: 38-05513 rev. *a page 11 of 14 switching waveforms (continued) zz mode timing [23,24] t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only ordering information speed (mhz) ordering code package name package type operating range 133 cy7c1351g-133axc a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1351g-133bgc bg119 119-ball bga 14 x 22 x 2.4 mm cy7c1351g-133axi a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack industrial cy7c1351g-133bgi bg119 119-ball bga 14 x 22 x 2.4 mm 117 cy7c1351g-117axc a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1351g-117bgc bg119 119-ball bga 14 x 22 x 2.4 mm cy7c1351g-117axi a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack industrial cy7c1351g-117bgi bg119 119-ball bga 14 x 22 x 2.4 mm 100 CY7C1351G-100AXC a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1351g-100bgc bg119 119-ball bga 14 x 22 x 2.4 mm cy7c1351g-100axi a100ra lead-free 100-lead 14 x 20 x 1.4 mm thin quad flat pack industrial cy7c1351g-100bgi bg119 119-ball bga 14 x 22 x 2.4 mm shaded areas contain advance information. please contain your loca l sales representative for more information on ordering these parts. lead-free bg package (ordering code: bgx) will be available in 2005. notes: 23. device must be deselected when entering zz mode. see truth ta ble for all possible signal conditions to deselect the device. 24. dqs are in high-z when exiting zz sleep mode.
preliminary cy7c1351g document #: 38-05513 rev. *a page 12 of 14 package diagrams 100-pin thin plastic quad fl atpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1351g document #: 38-05513 rev. *a page 13 of 14 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel and pentium are registered trademarks of intel corporation. zbt is a trademark of integrated device technology. nobl and no bus latency are trademarks of cypress semiconductor cor poration. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cy7c1351g document #: 38-05513 rev. *a page 14 of 14 document history page document title: cy7c1351g 4-mbit (128k x 36) flow-through sram with nobl? architecture document number: 38-05513 rev. ecn no. issue date orig. of change description of change ** 224360 see ecn rkf new data sheet *a 276690 see ecn vbl deleted 66 mhz changed tqfp package in ordering information section to lead-free tqfp added comment of availability of bg lead-free package

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